They are complementary to the DfM and test point placement rule checking features of commercial CIM systems. Specific customer requirements can be specified in a natural language using the custom rules feature. Electrical rules checking can validate company-specific DfT requirements in real time and are easily customized to reflect updates to testability guidelines.
Test Coverage Analysis Test coverage calculations for printed circuit boards PCBs are increasingly important as key indicators of product quality. In the majority of cases, PCB structural test strategies that include test and inspection techniques such as in-circuit test ICT , flying probe test FPT , automated optical inspection AOI , automated x-ray inspection AXI , or boundary scan test BST , are perfectly adequate in detecting the majority of manufacturing structural faults.
However, situations occur when optimum test coverage is not achievable through structural testing, or the current test strategy provides inadequate structural test coverage due to limited access. Under these circumstances it may be beneficial to evaluate the test coverage contribution provided by functional test FT to detect structural defects.
Typically, the defect universe comprises missing devices; wrong value, such as 10K instead of K; a dead device, e. Subsequently, we should categorize these defects in relation to a group of test coverage facets, providing a logical link with the production process.
It allows the model to be clearly understood by designers, project management, test engineers, and production operators. Supply of materials, placement of components, and soldering of components to the PCB determine correct manufacturing or the occurrence of process-induced defects.
The correlation between the defect universe defined by the various models and test coverage facets are shown in Table 1. Figure 2. Test Coverage Evaluation By reading the real test programs or coverage reports from the various test systems used within the manufacturing process, electrical DfT analyzers can control real versus theoretical test efficiency. PCBs come in three major types:.
The electronics industry drives toward more miniaturization, requiring design engineers to produce faster, smaller — and more complex — circuit board technology, which has a higher quality and costs less. It is important for a printed circuit board to perform its function and support the larger electronic device. Consequently, PCB manufacturers must have a system in place that monitors and tests each component to ensure that it meets various standards and delivers maximum performance.
When a component fails, analysts must utilize various processes, tools and techniques. With accuracy, they must determine why the device failed and how to prevent future failures. The following processes present unique challenges for electronics failure analysis:.
The fabrication of a complete PCB assembly requires an array of machines and materials, which include:. Some machines have automated features that perform checks at various points, and operators perform visual inspections before, during or immediately after the completion of a task.
Nonetheless, many PCBs will fail the final test. When a problem does occur, it is important to perform an effective electronics failure analysis in order to obtain clear and precise details about the source of the problem — and to ensure that it does not happen again. The technician must conduct a root cause analysis to identify the cause of the failure — not the symptoms — and take corrective action to fix the issue.
Failure analysis also provides invaluable feedback to design engineers on how to:. Any company that produces electronic hardware strives to achieve zero-defect production. To realize this objective, manufacturers must have the capability to perform some level of printed circuit board failure analysis. Some companies rely on outside expertise for more complex problems. For many high reliability systems — such as oil rigs, space satellites, implantable medical devices and other systems — failures can be devastating.
In the case of consumer products, a single failure mode, which can replicate thousands or millions of times, can have a huge impact on the bottom line.
Electronic device failure analysis provides a systematic process to help organizations investigate and understand why an electronic part failed.
Depending on the nature of the failure, an effective investigation can identify the failure mode, mechanism and elements, such as stresses inducing the failure and other issues. For example, solder joint defects make up a large percentage of PCB failures. Manufacturers can discover the root cause of the defective joints — such as a lack of solder paste, a gap between the PCB pad and component lead, or poor reflow profile — and then implement preventative measures.
To eliminate future failures, possible solutions may be to avoid solder paste contamination or ensure the correct aspect ratio. The methods used in the analysis depend on the severity of the failure and the type of issue. They can range from simple electrical measurements to the evaluation of sample cross-sections under a microscope. An effective and efficient root cause analysis ensures that manufacturers can initiate the necessary corrective action to prevent reoccurrence of the problem.
Failure analysis processes evaluate the reliability of a component product under operation and determine how to improve the product. There are a number of tests suitable for identifying defects. When the failure analyst understands the faults and how to prevent them, the company can improve the production process as well as the assemblies it manufactures. This technique employs a combination of external techniques, such as electrical testing, visual inspection, X-ray and cross-sectioning to the relevant area.
Micro-sectioning Analysis Micro-sectioning, sometimes called Cross-sectioning or Metallographic Preparation, refers to a PCB testing method used to investigate:.
The failure analyst removes a two-dimensional slice out of a sample, which uncovers features within the board. Considered a destructive testing method, micro-sectioning analysis provides the technician with a precise technique that isolates the relevant electronic component and removes the part from the PCB sample.
The technician puts the component into an epoxy resin or other potting medium and leaves it to cure and solidify. Some embodiments receive a set of model options , for example, from a user of the design environment , as part of a default configuration, etc.
The model options can define various types of threshold values, such as a maximum yield loss before a proposed design specification a is rejected.
Other model options can include selection of a Design Technology Class, which can impact the type of carrier used for the circuit assembly and the form factor for the circuit assembly, thereby potentially affecting how and where components can be populated. For example, different types of carriers may allow front-side and back-side component placement, the form factor of the carrier may constrain the space, rotation, and pitch of a particular component, etc.
Additionally, carrier selection may affect placement of components according to whether the carrier must be allowed to flex in certain locations by certain amounts, may affect which techniques can be used at different stages of production to check for types of defects, may affect which types of manufacturing processes can be used to populate components on the carrier e.
The Design Technology Class, or other model options , may define further constraints according to the type of technology being produced. For example, in a cell phone application, a circuit assembly may carry certain constraints as to form factor, power usage and heat dissipation, antenna placement and size, chassis grounding and location, cavity placement e. On the contrary, a circuit assembly with the same schematic functionality may carry different constraints when produced for a central industrial communications facility.
In addition to using the component parts and attributes modeled by the component modeler and any received model options , additional data may be used by the manufacturing process modeler Some embodiments of the manufacturing process modeler model the production process e. Process data may be mapped to the components modeled by the component modeler according to their respective attributes.
For example, a component type may be associated with a preferred process e. This association can, be determined according to its package type, lead type, heat dissipation requirements, manufacturing specifications, or in any other useful way.
A circuit assembly having many different components may be produced on a manufacturing line that uses multiple processes to populate the components. For example, a first subset of the components is populated to a printed circuit board using an SMT process, a second subset of the components is populated to the printed circuit board using wave soldering process, and a remaining subset of the components is populated to the printed circuit board using manual soldering.
Some embodiments of the manufacturing process modeler further model aspects of the production according to defect data from the defect data store of the data storage subsystem Mappings between defects and components can include mapping a particular lead type or component package type to a certain predicted frequency of occurrence of a particular defect.
Mappings between defects and processes can, for example, include mapping a particular soldering process or other manufacturing process to a certain predicted frequency of occurrence of a particular defect. Further, a particular defect and a frequency of occurrence can be mapped to the manufacturing process alone, or in conjunction with the Design Technology Class, form factor, carrier type, component attributes, etc.
The defect occurrence frequencies can be derived from testing, prediction models, manufacturing specifications, assumed default values, manufacturing feedback, or in any other useful way. In some implementations, the defect occurrence frequencies can be expressed in terms of defects per million opportunities DPMO , which can be calculated as 1,, times the number of defects divided by the product of the number of components and the number of opportunities per component.
When populated using its preferred default process of SMT, the defect data predicts 20, defects per million; when populated using wave soldering, the defect data predicts 24, defects per million; and when populated using manual soldering, the defect data predicts 6,, defects per million. However, there may only be one opportunity per component for the defect or multiple concurrent defects to occur in an SMT or wave soldering processes, while there may be an opportunity for a defect with each pin when manual soldering processes are used.
Accordingly, the DPMO for the component may be calculated as 4,, 4,, and 7, for the SMT, wave soldering, and manual soldering processes, respectively. In some embodiments, the defect data store includes standard defect codes to facilitate mapping of defect data. Certain embodiments of the manufacturing process modeler further model screening processes. For example, at different stages in the production of the circuit assembly, it may be possible to screen for various defects in one or more ways, including optically, electrically, mechanically, etc.
As the circuit assembly moves through the production line, certain defects may become easier or more difficult to detect. For example, addressing a defect may involve different amounts and techniques of repair, rework, etc. In various embodiments, defect codes e. Data relating to screening processes, manufacturing processes, and the like may be stored in the process data store of the data storage subsystem Some or all of the stages have associated component placements, associated screening processes, associated potential defect types and occurrence frequencies, etc.
In one illustrative line configuration, the circuit assembly passes in turn through a PiP system for paste printing, a system for top-side chip placement, a reflow system, a system for bottom-side chip placement and adhesion, a manual placement system, a wave soldering system, a manual soldering system, and a cleaning and finishing system.
Model information coming from the manufacturing process modeler and the component modeler can be considered as forming a comprehensive model of real-world production data for the circuit assembly, at least as it potentially affects production yield. This data can then be used by a yield predictor of the yield prediction environment to make different types of production yield predictions. The yield predictor can generate many different types of data. For example, as discussed above, the manufacturing process modeler can map different data to form defect occurrence frequency estimates.
Those estimates can then be rolled up to calculate predicted defects for a total production run for the circuit assembly, for a particular defect type, for a particular component or component package type, for a particular form factor or Design Technology Class, for a particular manufacturing process or line configuration, for a particular screening process, etc. Some implementations allow drilling down of yield estimates to look at DPMOs or estimated yield effects per defect type e.
According to some embodiments, the yield predictor generates a set of yield predictions based on variable conditions.
In one example, as discussed above, the manufacturing process modeler can generate different mapping data for components according to the form factor in which they are being placed. It may be desirable to generate a set of yield prediction results, each corresponding to a different form factor. In another example, as discussed above, the manufacturing process modeler can generate different mapping data for components according to which manufacturing processes are used to populate which components of the assembly.
It may be desirable to generate a set of yield prediction results, each corresponding to a different set of manufacturing processes e. As illustrated, embodiments of the yield prediction environment also include a report generator Results from the yield predictor can be sent to the report generator for various types of reporting.
For example, the report generator can generate human-readable reports, machine-readable reports, raw data, etc. Certain implementations also report various costs. For example, the yield prediction data can be used to derive costs associated with overall yield loss, costs to repair particular defect types at particular process stages, cost comparisons between form factors or manufacturing process selections, cost comparisons between component selections, etc.
In some embodiments, data from the yield predictor can also be fed back to the data storage subsystem to modify one or more types of data. The updated design parameters can be reflected in a revised proposed design specification a. If it is determined that the yield prediction results are satisfactory e. For example, the production design specification b may not include an electrical schematic and, instead, may include CAD drawings or numerical control code, manufacturing system settings, test parameters and procedures, etc.
One or more production manufacturing environments produces the circuit assembly products according to the production design specification b.
As part of production, the production manufacturing environment s record and maintain various types of information. For example, a production manufacturing environment can track actual yields over time, defects detected by screening processes, etc.
In some implementations, the production manufacturing environment s use standard defect codes that can easily be traced back to information used in the yield prediction environment As illustrated, the yield prediction environment may include a feedback processor Embodiments of the feedback processor receive feedback data from the production manufacturing environment s and pass the data to any or all of the yield predictor , the report generator , and the data storage subsystem For example, feedback data can be applied to data in the defect data store to tune defect predictions, feedback data can be used by the report generator to report predicted versus actual yields or predicted versus actual costs, etc.
It will be appreciated that functionality of the production environment , and its component sub-environments and functional component parts, can be implemented in various ways. The computational environment may be implemented as or embodied in single or distributed computer systems, or in any other useful way. The computational environment is shown including hardware elements that may be electrically coupled via a bus The hardware elements may include one or more central processing units CPUs , one or more input devices e.
The computational environment may also include one or more storage devices For the sake of illustration, the storage device s can include some or all of the data storage subsystem e. The computational environment may additionally include a computer-readable storage media reader a , a communications system e. As illustrated some or all of the functionality of the design environment and the yield prediction environment can be implemented as one or more modules in working memory In some embodiments, various data is communicated with other systems, like one or more production manufacturing environments , via a network It should be appreciated that alternate embodiments of a computational environment may have numerous variations from that described above.
Software of the computational environment may include code for implementing embodiments of the present invention as described herein. The systems described above with reference to FIGS. Any descriptions of those method embodiments that reference particular system components are intended only to add clarity to the description and should not be construed as limiting the scope of those embodiments.
Turning to FIG. The method begins at blocks by generating a schematic design for the circuit assembly. As discussed above, the output of block may include a design specification having schematic information and BOM information.
The design specification data can be sent to a yield prediction environment e. For example, embodiments include a component modeler for modeling components of the BOM along with their relevant attributes and a manufacturing process modeler for modeling a line configuration and screening processes and for mapping defect data. The various models can all be considered part of a yield prediction model that is used by the yield prediction environment to perform its yield prediction functionality.
Generating the yield prediction model can involve an iterative process between design functions and yield prediction functions. Further, the yield prediction model can be generated automatically as a function of the design specification and data maintained by the yield prediction environment, or portions of the model may be generated or adjusted manually. Further, the yield prediction model typically changes over the course of the design cycle to accommodate new information and new types of information.
For example, depending on the phase of the design cycle, the yield prediction model may include basic BOM information, complete parts list information with attributes, CAD data showing component placements, line configuration data, screening process data, etc.
At block , component placement strategies are outlined and evaluated. This may include auto-populating components according to defined rules e. In some embodiments, various options are outlined and evaluated at block For example, various form factor options are provided either manually or according to attribute or other data maintained by the yield prediction environment.
Reports may be generated to facilitate comparison of the different yield prediction results. Embodiments may allow for manual or automated selection of a preferred component placement strategy according to the yield prediction results. The preferred component placement strategy can include information generated in support of analyzing that strategy. At block , the preferred component placement strategy is used to execute component placement. As discussed above, some embodiments execute the component placement as part of the yield prediction environment e.
Notably, some or all of blocks - can be implemented as an iterative process e. In some embodiments, at the stage in the process where component placement is occurring, design for manufacture DFM issues may be largely ignored. Accordingly, a next stage of the design process may focus on DFM and related issues. At block , DFM and other process issues are analyzed according to the now-executed component placement. As discussed above, manufacturing processes can be assigned for each component, each component type, each packaging type, each sub-assembly, or in any other useful way.
Defects can also be mapped to various manufacturing process steps or other relevant data. In some embodiments, screening processes are assigned to detect defects at various stages of the production process. Certain implementations consider various process options that are provided either manually or according to attribute or other data maintained by the yield prediction environment. Each component may be associated with a preferred i.
Each process option may be associated with a different predicted frequency of defect occurrence. Further, different process options may allow for different types of screening, which may affect the cost of remediation of any detected defects, as well as potentially affecting yield loss. Evaluating the various options at block may involve comparing the different options with respect to estimated yield, defect types, cost of defect remediation, cost of manufacture e.
Reports may be generated to facilitate comparison of the different yield prediction results according to the different process options. Embodiments may allow for manual or automated selection of a preferred design specification according to the yield prediction results.
The preferred design specification strategy can include any useful information generated in support of analyzing that strategy. At block , the preferred design specification is used to generate or settle on a final proposed design specification e. Some or all of blocks - can be implemented as an iterative process e. In some embodiments, the final proposed design specification is promoted as the production design specification and is communicated to one or more production manufacturing environments for execution at block In other embodiments, the final proposed design specification, with all its associated component, process, and screening data, is passed through the yield prediction environment again for final evaluation and assessment at block In some cases, the assessment at block provides an opportunity to fine tune the design specification.
For example, component placements may be adjusted, screening processes may be evaluated, etc. The interaction between blocks and may, thus, involve one or more iterations. The final assessment may also be the stage in the design process at which costs are finally evaluated, in implementations where those costs are not addressed previously. In other cases, the assessment at block is used to generate a final report of yield predictions and related production design specification data e.
Having finalized the design and reported the final prediction and specification data, the resulting production design specification is communicated to one or more production manufacturing environments for execution at block As discussed above, some embodiments use feedback from the production manufacturing environments for various purposes. For example, the feedback data can be used to tune e. At block , the feedback data can be used to build analysis reports, tune yield prediction models, etc.
Accordingly, the method may iterate to block to execute production of the circuit assembly according to the most recent production design specification. As discussed above, some embodiments e. The method a begins at block by identifying a design specification for a circuit assembly that has a number of circuit components to be populated in the circuit assembly according to the design specification. For example, referring to FIG.
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